Charla: Designing HPC Architectures at the Barcelona Supercomputing Center

Localización: Aula A.01, Ed. Ada Byron

Fecha y hora: 29 de Mayo de 2018 a las 12:00


El próximo martes, 29 de Mayo, nos visita Miquel Moreto de la UPC/BSC para impartir la siguiente charla: 

Title: Designing HPC Architectures at the Barcelona Supercomputing Center

Speaker: Miquel Moreto, UPC/BSC


Abstract: In the last decade, the traditional ways to keep the increase of hardware performance to the rate predicted by Moore's Law vanished. Multi-core processors helped maintaining performance improvements for a while, but they still have to face multiple problems in terms of power consumption, programmability, resilience and memory. To overcome these challenges, a promising approach is to give more responsibility to the runtime system and to let it tightly collaborate with the hardware. In fact, we believe that the runtime system has to drive the design of future multi-cores architectures. 

In this talk, we will introduce an approach towards a Runtime-Aware Architecture (RAA), a massively parallel architecture designed from the runtime's perspective. Also, we will explain the potential impact of RAAs in the context of the European Processor Initiative, a flagship European project that will design and deploy an Exascale supercomputer using European processors.



Bio: Miquel Moreto is a Ramon y Cajal researcher at UPC and associate researcher at the Barcelona Supercomputing Center (BSC), Spain. He received the BSc and MSc degrees in mathematics and electrical engineering from UPC, and the PhD degree in 2010 in the Computer Architecture Department at the same university. He was a Fulbright postdoctoral fellow at the International Computer Science Institute (ICSI), affiliated with UC Berkeley, USA, from 2012 to 2013. In 2013, he joined the BSC to work on the ERC-funded project RoMoL and the Mont-Blanc 3 H2020 European project. His research interests include high performance architectures and hardware-software co-design for future massively parallel systems.